Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and non-volatile (e.g., flash) memory.
Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Changes in threshold voltage of the cells, through programming of a charge storage structure, such as floating gates, trapping layers or other physical phenomena, determine the data state of each cell.
Due to ever increasing system speeds, memory manufacturers are under pressure to increase the bandwidth of their memory devices so that the memory does not become a speed bottleneck for the system. Memory manufacturers are also under pressure to constantly increase the memory density of the memory devices while maintaining, or even shrinking, the memory device size.
One way to increase both memory bandwidth and density is a three-dimensional structure in which strings of memory cells are fabricated vertically. FIG. 1 illustrates a cross-sectional view of a vertical memory cell string 120, 121 that preceded the present application.
An oxide 101 is formed on a source 100, which in this embodiment is conductively doped polysilicon. A level (e.g., layer) of conductively doped polysilicon (e.g., p-type polysilicon) 102 can be used as a gate of a select gate source (SGS) transistor for the string of memory cells 120, 121. An etch stop 103 is formed over the level of polysilicon 102, such as one that can be used during the process for forming the string 120, 121 to provide an etch resistance for the level of polysilicon 102 in order to slow the etching process in a future etching step.
Alternating levels 104-114 of an oxide 104, 106, 108, 110, 112 and conductively doped polysilicon (e.g., n-type polysilicon) 105, 107, 109, 111, 113 are formed over the etch stop 103. The levels of polysilicon 105, 107, 109, 111, 113 can be used as the control gates for the memory cells of the string of memory cells 120, 121. The levels of oxide 104, 106, 108, 110, 112 can be used to insulate control gates of adjacent memory cells. A level of conductively doped polysilicon (e.g., p-type polysilicon) 115 is formed on top of the last level of oxide 114. The level of polysilicon 115 can be used as a gate of a select gate drain transistor for the string of memory cells. Recesses of approximately 25 nm are formed into levels of the polysilicon 105, 107, 109, 111, 113.
For purposes of clarity, the following continued description of FIG. 1 focuses on only one memory cell 140 of string 120, 121. A recess is lined with an interpoly dielectric (IPD) 150 and filled with conductively doped polysilicon 130. A tunnel dielectric 151 is formed (e.g., grown or deposited) adjacent to the polysilicon 130. A pillar of semiconductor material (e.g., conductively doped polysilicon) 116 is formed through the level of polysilicon 115, the alternating levels of oxide and polysilicon 104-114, the etch stop 103, the level of polysilicon 102, and the oxide 101, with the pillar of polysilicon 116 being adjacent to the tunnel dielectric.